Nov 20, 2014

Wafer Bonding: Key Enabling Technology for Photonic Integration

Abstract: Over the last decade, wafer bonding has become a very powerful technology for MEMS/MOEMS manufacturing. Being able to offer solutions to overcome standard materials integration processes (e.g. epitaxy, thin film deposition), wafer bonding is now considered an important item in the MEMS engineer toolbox. It is also becoming increasingly important for developments in photonic integration. Different principles governing the wafer bonding processes will be reviewed in this contribution and different types of applications will be presented as examples.

Introduction to Wafer BondingWafer bonding emerged during past decade as a powerful process technology supporting applications in the area of Micro- Electro- Mechanical Systems (MEMS), Micro- Opto- Electro- Mechanical Systems, photonic as well as 3D integration. Despite its increasing importance, there is still a certain level of ambiguity surrounding the term “wafer bonding”, especially because this general term covers several different processes that lead to the same target of joining two substrates but use very different principles. Figure 1 presents a possible classification of wafer bonding processes.
     Direct wafer bonding (known also as “fusion bonding” [1], “molecular bonding” [2]) is a process for which the adhesion between two surfaces occurs as a result of chemical bonds established between molecules from the two surfaces. Typically the adhesion is weak at room temperature (mediated only by Van der Waals forces) and maximum bond strength is reached by transforming the weak bonds into covalent bonds during a high temperature thermal annealing.
Figure 1. Wafer bonding categories grouped by bonding principle.
     One particular category of direct bonding is the surface activated wafer bonding. This process uses a special surface preparation process (surface activation) in order to change and control the bonding mechanism by controlling the surface chemistry. After surface activation, bonds (even covalent) with higher energy compared to the non-activated surfaces are formed at room temperature and thus the energy required to reach the maximum bond strength by forming covalent bonds across the entire interface is lower. As a result, the annealing temperature and annealing time in this case are much lower than in a standard direct bonding process. The annealing temperature for this type of process ranges from room temperature to 400°C, depending on materials to be bonded.
     Surface activation can be performed by a dip of the substrates in chemical solutions depending on the nature of the substrates (wet activation) or by a plasma treatment of the surface (dry activation).
     Plasma activated wafer bonding has been studied since the 1990s. Different research groups studied the bonding mechanism for wafers exposed to plasma inside etching equipment modified in order to obtain the surface activation effect [4, 5]. More recently, dedicated equipment was developed for the specific process step of plasma activated wafer bonding [5-7].
     Anodic wafer bonding (also known as “field assisted bonding” [8] or “electrostatic bonding” [9]) is also considered a direct bonding process even if the final bond is produced due to the growth of a bonding layer. Initially reported for joining a metal surface to a glass surface [8], the term “anodic bonding” is used today mainly to identify the bonding of silicon wafers to glass wafers with high alkali oxide content (the glass materials mostly used for anodic bonding are Borofloat® (from Schott Glass Germany), and Pyrex®7740 (from Corning Inc., USA)).
     The bond occurs when the two wafers are heated after being brought in contact and an electric field is applied. At a certain temperature (depending on the glass composition) oxides dissociate and the mobile alkali ions are driven by the electric field into the glass, creating an oxygen rich layer at the silicon-glass interface. Oxygen ions are driven by the electric field to the silicon surface where they produce oxidation. The resulting bond strength is very high and the process is irreversible.
     In the Eutectic wafer bonding process [10,11] the adhesion between two substrates occurs by forming a eutectic alloy at the interface, acting as bonding layer. For this process, the right metal scheme is deposited onto the surfaces prior to bonding.
     The main eutectic alloys used for wafer bonding are Au:Sn (280°C eutectic temperature), Au:Si (363°C eutectic temperature), Ge:Si (350°C eutectic temperature) and Al:Ge (423°C). In thermo-compression bonding [12,13] the two surfaces adhere to each other due to a metal bond established between the atoms from two metal surfaces pressed together under heating. This type of bond is used mainly when electrical interconnections between the two wafers are required, though some groups use it for vacuum applications because there is no material outgassing during the bonding process.
     Glass frit wafer bonding [14,15] is using as an intermediate layer for the bonding of low melting point glasses. The bond occurs by heating the substrates with applied contact force.
     This process is very reliable and is used in high volume production by major MEMS devices manufacturers for applications where low vacuum encapsulation is required. Adhesive wafer bonding [16-18] (known also as “polymer bonding” [19]) uses an intermediate layer for bonding. Evaporated glass, polymers, spin-on glasses, resists, and polyimides are some of the materials suitable for use as intermediate layers for bonding. The choice of intermediate layer material is always made considering the substrate materials and topography.
     The main advantages of this approach are: low temperature processing (maximum temperatures below 400°C), surface planarization, and tolerance to particles (the intermediate layer can incorporate particles with diameter comparable to the layer thickness).
     The wafer bonding processes briefly described here are the most commonly used in applications. Except for direct (fusion) bonding, all of the techniques can be considered low temperature processes. The need for low temperature is mainly imposed by the thermal mismatch of the materials used for bonding. By keeping the process temperature as low as possible, the stress generated by the different thermal expansion of the materials is not completely compensated but it can be decreased to an acceptable range which allows successful bonding.

Wafer Bonding ApplicationsSome of the specific features of wafer bonding that make it valuable for various applications are:
  • process is not restricted to a certain category of material (applicable to semiconductors, metals, glass, polymers, etc.);
  • if bonding partners are single-crystalline, their lattices do not have to match (as in the case of epitaxially grown wafers); only their surfaces have to meet flatness, smoothness, and cleanliness requirements;
  • processes are applicable at wafer level (depending on materials, up to 300 mm diameter), which increases manufacturing efficiency and opens new horizons in processes with high costs (e.g. moving from chip-level packaging to wafer level packaging in MEMS).
     With the development of low temperature (up to 400°C) fusion bonding methods, the application area of this process is greatly expanded.
     One example of an emerging application area is silicon photonic integrated chips [20,21]. This application uses wafer bonding for compound semiconductor – silicon integration.
     The result of this work was the fabrication of the first InGaAsP-based Multiple Quantum Well (MQW) hybrid Si evanescent racetrack-shaped lasers.
     Silicon photonics is a promising solution for high speed optical interconnects for future microprocessors. Silicon transparency in the fiber optic telecom window (wavelength: 1.3 – 1.6 µm) is an important reason for considering microphotonics and microelectronics integration. The intrinsic low radiative recombination efficiency of the crystalline Si due to its indirect bandgap leads to two major integration approaches to build active optoelectronic components on Si. The first is monolithic compound semiconductor-on-Si heteroepitaxial growth. The large lattice mismatch between Si and GaAs (4%) or InP (8.1%) is a major challenge for fabrication of layers with low levels of dislocations. The second approach is based on wafer bonding and uses the fact that lattice mismatch is not conditioning wafer bonding success, thus enabling the combination of bulk quality Si and compound semiconductors.
     If the crystallographic properties of the two materials to be combined does not play any role in wafer bonding, the main limitation of this process consists of the usually very different thermal expansion coefficients of the two materials. As an example, in case of Si and GaAs direct wafer bonding, the thermal expansion of GaAs is double that of Si. This fact will result in very high stress at the interface between the two materials, leading to separation (debonding) or even to GaAs substrate breakage.
     One of the solutions for overcoming thermally induced stress is the use of an intermediate bonding layer. As some applications require direct contact of the two materials, with no intermediate bonding layers, this solution is not applicable when direct coupling is required through bonding.
     For this type of application new processes were developed. In such a process flow, the two surfaces are exposed to a plasma prior to being placed in contact (figure 2).

Figure 2. Schematic process flow of plasma activated wafer bonding process.

     In the first step surfaces can be prepared for bonding using a wet chemical etching of native oxides on the two surfaces. After native oxide chemical removal both wafers are activated with an O2 plasma in a commercial EVG®810LT LowTemp Plasma Activation instrument. Wafers are then cleaned with deionized water, which also serves as the final surface activation step to terminate the surface with hydroxyl (–OH) groups. After 15 hours thermal annealing in an oven at 300°C, the 635-µm-thick InP substrate is selectively removed in a HCl:H2O (3:1) solution, resulting in only ~2 µm thick epitaxial layer on the SOI substrate. A crack-opening measurement indicates that the bonding surface energy exceeds the fracture energy of the bulk InP material.
     A bonding yield higher than 95% was achieved in this case and MQW laser diode structures evaluation showed no change in performance after wafer bonding process.
     Another very important wafer bonding-based application is the fabrication of back-side illuminated CMOS sensors.
     In order to overcome the pixel area limitation by the metal interconnects in CMOS image sensors, the backside has to be “open” for the light after wafer processing.
     One of the most convenient process flows consists of:
  • Sensor fabrication in CMOS technology
  • CMOS wafer bonding to a blank Si wafer (usually named handle or carrier)
  • Back-thin CMOS wafer (typically by grinding and etching or polishing)
  • Fabricate the camera objective (add colour filters, lenses, etc.)
     Two different wafer bonding processes are currently competing for this type of process:
  • Low temperature plasma activated bonding fusion bonding;
  • Adhesive wafer bonding using a polymer as bond layer.
     The two processes have different process flows:
     In the first approach, the CMOS wafer has to be planarized (made flat) in order to meet the requirements of fusion bonding (process flow shown in figure 3).

Figure 3. Back-Side Illuminated CMOS image sensor fabrication flow based on plasma activated wafer bonding.

     In order to obtain the flat surface for bonding, the CMOS wafer goes first through a
planarization process consisting of silicon oxide deposition (e.g. PECVD, TEOS) followed by oxide layer densification in order to remove gas from oxide layer (typically a thermal annealing in vacuum at 300°C – 400°C) and oxide layer polishing using a standard Chemical Mechanical Polishing (CMP) process.
     After CMOS planarization the wafers are plasma activated and aligned using either edge-to-edge alignment (maximum accuracy: ±50 µm) or optical alignment (maximum accuracy: <1 µm). Wafers are typically brought into contact at room temperature for spontaneous bonding and then thermally annealed at temperatures of 200°C – 400°C.
     After the wafer bonding step the initial CMOS substrate is back-thinned using grinding and etching, then the entire sensor structure is completed by specific steps (e.g. adding colour filters).
     In the end, the final sensor structure fabrication at wafer level is completed by adding the optical elements (lenses, filters, spacers between optical elements). This part of the process can also be completed by wafer bonding processes: in this case the process of choice is typically adhesive wafer bonding based on UV-curable polymers. This process is very effective and is done at room temperature, which minimized the risk of adding stress to the already built multi-layered structure.
     The second process used for such application, adhesive wafer bonding, is presented in
figure 4.

Figure 4. Back-Side Illuminated CMOS image sensor fabrication flow based on adhesive wafer bonding with polymer layers.

     In this alternative process flow, the planarization of CMOS wafer is accomplished by the polymer bonding layer. It is known that polymer materials can fill gaps, compensate flatness variations and even incorporate particles with diameters comparable to the polymer layer thickness.
     The process flow is simplified in this case compared to the plasma activated bonding approach by replacing the planarization with oxide with a polymer spin- or spray-coating process.
     However, when choosing a wafer bonding process for this application a few different aspects have to be compared.

Process Flow Type
Plasma Activated Fusion Wafer Bonding
Adhesive Wafer Bonding
Max. bonding temperature
200°C – 400°C
150°C – 300°C
Oxide deposition Densification CMP
Alignment accuracy
Low (edge-to-edge)
or high (<1 µm)
Medium-high (2–10 µm)
Compatibility class
Table I. BSI CMOS sensors: plasma activated bonding vs. adhesive bonding.

ConclusionThe increasing number of new applications in the areas of microelectronics, microphotonics and MEMS/MOEMS is requiring the development of new processing technologies as well as the optimization of already known ones. Wafer bonding is an example of technology which gains an increasing importance due to some important specific features. With Silicon-on-Insulator (SOI) substrate fabrication being for a long time almost the only high volume manufacturing application of bonding, today we are facing an increasing number of applications including areas as microelectronics (e.g. wafer-level 3D integration based on Through-Si Vias – TSV – and wafer bonding), microphotonics (e.g. microring resonators fabrication using wafer bonding process [22]), as well as numerous MEMS – type sensors (e.g. pressure sensors, gyroscopes for handheld products). Due to its high flexibility, wafer bonding offers a valuable solution in materials and photonics integration as well as cross-integration of different technologies (e.g. microelectronics and microphotonics or microelectronics and optics). The new developments in low temperature processing have significantly expanded the area of applications of wafer bonding.
  1. S. Weichel, F. Grey, K. Rasmussen, M. Nielsen, R. Feidenhans’l, P. B. Howes, and J. Vedde, Appl. Phys. Lett. 76 (1), pp. 70, 2000.
  2. F. Fournel, H. Moriceau, B. Aspar, K. Rousseau, J. Eymery, J. L. Rouviere, and N. Magnea, Appl. Phys. Lett. 80 (5), pp. 793, 2002.
  3. D. Pasquariello and K. Hjort, IEEE J. on Sel. Topics in Quant. Electronics 8 (1), pp. 118, 2002.
  4. M. Reiche, M. Wiegand, and V. Dragoi, Electrochem. Soc. Proc. Series, vol. PV99-35, pp. 292, 1999.
  5. V. Dragoi, P. Lindner, S. Farrens, and J. Weixlberger – Proc. of Int. Semicond. Conf. – CAS 2004, IEEE Proc. 04TH8748, vol. 1, pp. 199.
  6. M. M. R. Howlader, H. Okada, T. H. Kim, T. Itoh, and T. Suga, J. Electrochem. Soc. 151 (7), G461, 2004.
  7. M. Gabriel, B. Johnson, R. Suss, M. Reiche, and M. ­Eichler – Proc. of COMS 2004 – 9th Int Conf. On Commerciallization of Micro and Nano Systems, 2004, pp. 353.
  8. G. Wallis and D. Pommerantz, J. Appl. Phys. 40, p. 3946, 1969.
  9. A. Cozma and B. Puers, J. Micromech. and Microeng. 5, pp. 98, 1995.
  10. R. F. Wolffenbuttel – Sensors & Actuators A62, pp. 680, 1997.
  11. K. T. Turner, R. Mlcak, D. C. Roberts, and S. M. Spearing –
    MRS Spring Meeting 2002, MRS Proc. Series, vol. 687, pp. B. 3.2.1., 2002.
  12. C. H. Tsau, S. M. Spearing, and M. A. Schmidt, J. of Microelectromech. Systems 11 (6), pp. 641, 2002.
  13. A. Fan, A. Rahman, and R. Reif – Electrochem. & Solid-State Lett. 2 (10), pp. 534, 1999.
  14. Y. Jin, Z. F. Wang, P. C. Lim, D. Y. Pan, J. Wei, and C. K. Wong – Proc. of Int. Electronic Pack. Tech. Conf. – EPTC, 2003, IEEE Proc. Series, pp. 301.
  15. S. Sridharan, J. Henry, J. Maloney, B. Gardner, K. Mason, V. Dragoi, J. Burggraf, E. Pabo, and E. Cakmak, MRS Proceedings Series, vol. 1139, 1139-GG03-35.
  16. V. Dragoi, T. Glinsner, G. Mittendorfer, B. Wieder, and P. Lindner, SPIE Proc. Series vol. 5116, p. 160, 2003.
  17. Y. Kwon, A. Jindal, J. J. McMahon, J.-Q. Lu, R. J. Gutmann and T. S. Cale, MRS Spring Meeting 2003, MRS Proc. Series vol. 766, pp. E5.8.1., 2003.
  18. J. Oberhammer and G. Stemme – J. of Microelectromech. Systems 14 (2), pp. 419, 2005.
  19. P. P. Absil, J. V. Hryniewicz, B. E. Little, F. G. Johnson, K. J. Ritter, and P.-T. Ho, IEEE Phot. Techn. Lett. 13 (1), pp. 49, 2001.
  20. H. Park, A. W. Fang, S. Kodama, and J. E. Bowers, Opt. Exp. 13, pp. 9460, 2005.
  21. D. Liang, A. W. Fang, D. C. Oakley, A. Napoleone, D. C. Chapman, C.-L. Chen, P. W. Juodawlkis, O. Raday, and J. E. Bowers, Electrochem. Soc. Trans.16 (8), pp. 235, 2008.
  22. V. Dragoi, M. Alexe, M. Hamacher, and H. Heidrich, Electrochem. Soc. Trans.16 (8), pp. 105, 2008.

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