Apr 16, 2020

Single Crystal Silicon Thin Film on Polymer Substrate by Double Layer Transfer Method

We report discovery of new method to transfer a single crystal silicon thin film onto a bendable polymer substrate by using layer transfer process. The method includes creation of mechanically weakened layer 100 nm - 600 nm below the Si wafer surface using boron and hydrogen ion implantations. Silicon mother wafer is then pre-bonded to glass and exfoliated. Exfoliation divides the glass-silicon assembly into weakly bound Si thin film on glass and leftover mother Si wafer. Then the silicon thin film was transferred from glass substrate into a polymer substrate.

Source:IOPscience

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Apr 9, 2020

Coplanar Integration of Lattice-Mismatched Semiconductors with Silicon by Wafer Bonding Ge / Si1 − x Ge x  / Si Virtual Substrates

We have demonstrated a general process which could be used for the integration of lattice-mismatched semiconductors onto large, Si-sized wafers by wafer bonding  virtual substrates. The challenges for implementing this procedure for large diameter Ge-on-insulator (GOI) have been identified and solved, resulting in the transfer of epitaxial  to a Si wafer. We found that planarization of Ge virtual substrates was a key limiting factor in the transfer process. To circumvent this problem, an oxide layer was first deposited on the Ge film before planarization using a standard oxide chemical mechanical planarization process. The GOI structure was created using -induced layer exfoliation (Smartcut™) and a buried  etch-stop layer, which was used to subsequently remove the surface damage with a hydrogen peroxide selective etch. After selective etching, the crosshatched surface morphology of the original virtual substrate was preserved with roughness of <15 nm rms as measured on a  scale and a  scale roughness of  Using an etch-stop layer, the transferred device layer thickness is defined epitaxially allowing for future fabrication of ultrathin GOI as well as III-V films directly on large-diameter Si wafers. © 2004 The Electrochemical Society. All rights reserved.

Source:IOPscience

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Apr 2, 2020

Large area stress free Si layer transfer onto Corning glass substrate using ion-cut

We report on the large area stress free single crystal silicon (Si) layer transfer onto glass substrate using hydrogen ion (H+) implantation and heterogeneous direct wafer bonding (DWB) (ion-cut process). Si wafers were implanted with H+ ions at room temperature followed by the DWB between the Si wafer and glass substrate. Post-implantation annealing studies were performed at different temperatures. The root mean square surface roughness of the H-implanted Si wafer and glass substrate was measured to be 0.3 nm and 0.5 nm, respectively. At an annealing temperature of 330 °C, a thin layer of the Si wafer was transferred onto the glass substrate. The average thickness of the transferred layer was found to be ~605 nm with surface roughness of 4 nm. Raman spectroscopy confirmed that the transferred Si layer was stress free and retained its crystallinity. Large area transfer of high quality stress free Si-on-glass substrate is demonstrated using heterogeneous DWB and ion-cut process.

Source:IOPscience

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Mar 26, 2020

A new method for measuring the flatness of large and thin silicon substrates using a liquid immersion technique

Flatness measurements of thin and large substrates are greatly affected by gravity. In this work, a new method was proposed for accurately measuring the flatness error of large and thin silicon wafers using a floating technique. In this method, a silicon wafer was immersed in a liquid that had a density slightly lower than that of silicon and was supported by three ball supporters in the liquid. The wafer shape was measured using a laser triangulation sensor. The buoyancy force on the wafer inside the liquid could cancel out most of the effect of gravity. The residual effect of gravity was further removed by subtracting the residual deflection calculated by finite-element modeling from the measured result. The method was validated by comparing the flatness values of a thick wafer measured using this method and via a commercially available interferometer. The deformations of wafers ground by #600 and #2000 diamond wheels were measured and the measurement error was less than 3% of the total deformation.

Source:IOPscience

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Mar 19, 2020

Wafer-scale analysis of GaN substrate wafer by imaging cathodoluminescence

With the progress in large-size high-quality GaN substrates, wafer-scale analysis is needed to evaluate homogeneity and defect distribution. We demonstrate the mapping of a 2 inch GaN substrate wafer based on the imaging cathodoluminescence technique. Macro pit defects with sizes varying from microns to millimeters are visualized and classified into three types according to their optical and structural properties. The formation mechanisms of the different types of pit defects are discussed with consideration of the facet growth involved in substrate growth.

Source:IOPscience

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Mar 12, 2020

Characterization of the Descum Process for Various Silicon Substrates Doping

The descum process is temperature-sensitive process. It has been demonstrated that the process is very sensitive to silicon substrate doping, which impacts wafer heating. A higher doping level caused much higher resist removal when the descum process was ran in a reactor that also ran dry strip processes. The higher level of resist removal was the result of higher wafer surface temperature. The likely causes for higher wafer surface temperature are lower thermal conductivity and higher emissivity of the highly doped wafer substrate.

Source:IOPscience

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Feb 28, 2020

Investigation of Various Substrate Dopants and Epitaxial Growth Techniques for Producing Sharp Transition Epitaxial Wafers

Arsenic, antimony, phosphorus, boron, and gallium doped silicon substrates were used for the fabrication of n/n+ or p/p+ epitaxial wafers to study autodoping effects in a horizontal induction heated atmospheric pressure epitaxial reactor. Using the "high‐low" technique which uses a high temperature prebake (without  etching) followed by a relatively low temperature and slow growth rate deposition, sharp n/n+ transition on arsenic material was achieved. This method appears to produce an epitaxial layer of more uniform resistivity out to the beginning of the transition region for all of the n‐type substrates used. This is indicative of reduced autodoping effects. Results show that when the epitaxy employs the high‐low technique at a temperature of 1050°C, heavily doped arsenic substrates offer unique transition and defect density advantages over either antimony or phosphorus material. This should enable a reduction in n/n+ epitaxial layer thickness. The high‐low technique did not reduce autodoping for the p‐type substrates. The gallium substrates evaluated during these experiments exhibited unexpected behavior in light of the fact that gallium has a diffusion constant nearly identical to that of boron at 1100°C. However, the gallium wafers showed little difference in transition between any of the deposition conditions tried. Extreme gas phase autodoping is believed to be the cause for these gallium doped substrate results.

Source:IOPscience

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